This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes.  It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package.

Artur Balasinski is a Technology Design Integration Manager for Cypress Semiconductor in San Jose, California.

Introduction.- 2D DfM.- 3D DfM.- 4D DfM.- Correlation to Rule of 10.- X-fab manufacturability and sharing.