Beschreibung
Inhaltsangabe1. Introduction and History; R.W. Brodersen. Part I: Framework and Design Entry. 2. The OCT Data Manager; R. Spickelmier, B.C. Richards. 3. Lager OCT Policy and the SDL Language; B.C. Richards. 4. Schematic Entry; B. Reese. 5. Design Management; B.C. Richards. 6. Design Post-Processing; M. Thaler, B.C. Richards. Part II: Silicon Assembly. 7. Hierarchical Tiling; J. Sun, B.C. Richards. 8. Standard Cell Design; B. Reese, B. Boes. 9. Interactive Floorplanning; Seungjun Lee, J. Rabaey. 10. Datapath Generation; M. Srivastava. 11. Pad Routing; E. Lettang. Part III: Verification and Testing. 12. Design Verification; Wun-Tsin Jao, R. Jain. 13. Behavior and Switch Level Simulation; L. Svensson, L.E. Thon, Seungjun Lee. 14. Chip and Board Testing; K.T. Kornegay. Part IV: Behavioral Synthesis. 15. DSP Specification Using the Silage Language; P. Hilfinger, J. Rabaey. 16. Synthesis of Datapath Architectures; J. Rabaey, Chin-min Chu, Phu Hoang, M. Potkonjak. 17. From C to Silicon; L.E. Thon, K. Rimey, L. Svensson. 18. An FIR Filter Generator; P. Yang, R. Jain. Part V: Applications. 19. The PUMA Processor; L.E. Thon. 20. Radon Transform Using the PPPE; W.B. Baringer. 21. Speech Recognition; A. Stölzle. 22. Conclusions and Future Work; R.W. Brodersen. Appendix A: Design Example; B.C. Richards. Appendix B: Training and Distribution; B. Reese. Index.
Inhalt
1. Introduction and History; R.W. Brodersen. Part I: Framework and Design Entry. 2. The OCT Data Manager; R. Spickelmier, B.C. Richards. 3. Lager OCT Policy and the SDL Language; B.C. Richards. 4. Schematic Entry; B. Reese. 5. Design Management; B.C. Richards. 6. Design Post-Processing; M. Thaler, B.C. Richards. Part II: Silicon Assembly. 7. Hierarchical Tiling; J. Sun, B.C. Richards. 8. Standard Cell Design; B. Reese, B. Boes. 9. Interactive Floorplanning; Seungjun Lee, J. Rabaey. 10. Datapath Generation; M. Srivastava. 11. Pad Routing; E. Lettang. Part III: Verification and Testing. 12. Design Verification; Wun-Tsin Jao, R. Jain. 13. Behavior and Switch Level Simulation; L. Svensson, L.E. Thon, Seungjun Lee. 14. Chip and Board Testing; K.T. Kornegay. Part IV: Behavioral Synthesis. 15. DSP Specification Using the Silage Language; P. Hilfinger, J. Rabaey. 16. Synthesis of Datapath Architectures; J. Rabaey, Chin-min Chu, Phu Hoang, M. Potkonjak. 17. From C to Silicon; L.E. Thon, K. Rimey, L. Svensson. 18. An FIR Filter Generator; P. Yang, R. Jain. Part V: Applications. 19. The PUMA Processor; L.E. Thon. 20. Radon Transform Using the PPPE; W.B. Baringer. 21. Speech Recognition; A. Stölzle. 22. Conclusions and Future Work; R.W. Brodersen. Appendix A: Design Example; B.C. Richards. Appendix B: Training and Distribution; B. Reese. Index.
